Beschreibung
InhaltsangabeForeword. Preface. 1. Introduction. Part I: Equivalence Checking. 2. Symbolic Verification. 3. Incremental Verification for Combinational Circuits. 4. Incremental Verification for Sequential Circuits. 5. AQUILA: A Local BDD-Based Equivalence Verifier. 6. Algorithm for Verifying Retimed Circuits. 7. RTL-to-Gate Verification. Part II: Logic Debugging. 8. Introduction to Logic Debugging. 9. ErrorTracer: Error Diagnosis by Fault Simulation. 10. Extension to Sequential Error Diagnosis. 11. Incremental Logic Rectification. Bibliography. Index.
Produktsicherheitsverordnung
Hersteller:
Springer Verlag GmbH
juergen.hartmann@springer.com
Tiergartenstr. 17
DE 69121 Heidelberg
Inhalt
Foreword. Preface. 1. Introduction. Part I: Equivalence Checking. 2. Symbolic Verification. 3. Incremental Verification for Combinational Circuits. 4. Incremental Verification for Sequential Circuits. 5. AQUILA: A Local BDD-Based Equivalence Verifier. 6. Algorithm for Verifying Retimed Circuits. 7. RTL-to-Gate Verification. Part II: Logic Debugging. 8. Introduction to Logic Debugging. 9. ErrorTracer: Error Diagnosis by Fault Simulation. 10. Extension to Sequential Error Diagnosis. 11. Incremental Logic Rectification. Bibliography. Index.
